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TC90A92AFG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC90A92AFG
3D comb & Video Decoder
TC90A92AFG is a 1chip LSI of 3 dimensional Y/C separation and color decoder. TC90A92AFG has 10bit A/D converter and 8bit A/D converter for analog Video signal and 1H component signal. and it also has 4Mbit DRAM for NTSC 3D comb. In case of PAL system, 3 line comb is available. The internal color decoder is adaptive to multi color system.
Feature * Multi color system * Input I/F *F CVBS / S / YCbCr * 3DYCS *F NTSC system * 3lineYCS+3D YNR/CNR : Multi color system *i SECAM*F YCS*j BPF * Output I/F *F / 601 656 * Picture improvement Y *F Vertical enhance / LTI / Contrast / Set up adjust C *F TOF / ACC / Color decode / Color gain /CTI / offset adjust * S/N detection / ID1 data slice / CCD data slice * I C bus control * Package*F QFP 100 * Power supply*F 1.5V*C 2.5V*C V 3.3
2
QFP100-P-1420-0.65Q Mass : 1.6g (TYP)
Version 1.5
TOSHIBA is continually working to improve the quality and the reliability of its product. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.
TC90A92AFG
1. Block diagram
HD/VD
D/A Sync Sep. Clamp 27M 10bit ADC ID1 S/N detection CCD slice 27M *4fsc 42M X'tal
Timing
*~ 8
Clock Gene.
reference clock Vertical enhance
3line comb
LTI
contrast adust delay adjust b b color decord m h s s adjust Color adjust ITU-R656 e n c o d...
CVBS/Y
4M
DRAM
3D comb Motion Det.
656/601 Format
C
MPX
Cb Cr
27M 8bit ADC IIC-BUS
Digital *@ I/F
SW
SCL SDA
2. Pin layout
NCO DAC Analog input I/F VRTCAD BIASCAD VRBYAD VDDYAD VSSYAD VRMYAD VRTYAD BIASYAD
CIN
1 VDDPLL 2 PLLIN 3 VCOFIL 4VSSPLL 5VDDXO 6 XOIN 7 XOOUT 8 VSSXO 9 BUSSEL TC90A92AFG 10 DVDD1 11 DIN9 12 DIN8 Top view 13 DIN7 14 DVSS12 15 DIN6 16 DIN5 17 DVDD2 18 DIN4 19 DIN3 20 VSSRAM1 21 VDDRAM1 22 DIN2 23 DIN1 24 VDDIO1 CSYNC IN
25DIN0 26GC14IN 27 VSSIO1 28 TESTIN 29 TESTM0 30 RESET
YIN
10 9 8 7 6959493929 1 0 9 887868584838281 988 09 9 9 9 80 YCLAMPP 79 VBI READY UVFLAG 78 OEPK 77 76 VDOUT 75 HDOUT 74 COUT9 73 DVSS5 72 COUT8 COUT7 71 DVDD5 70 69 COUT6 68 COUT5 67 VSSIO3 66 COUT4 65 COUT3 VDDIO3 64 63 COUT2 DVSS4 62 COUT1 61 60 COUT0 59 DVDD4 58 CKOUT YOUT0 57 56 YOUT1 55 YOUT2 54 YOUT3 53 VDDRAMD1 52 VSSRAMD1 51 VDDRAM2
42M XO X8PLL
VDDDA VRBCAD Cb IN VSSCAD Cr IN VDDCAD
VREFDA BIASDA VSSDA
DAOUT
Digital inut I/F
DVSS3 TESTM5 TESTM6 VDDIO2 YOUT9
TESTM1 TESTM2 TESTM3 DVDD3 TESTM4
SDA SCL
3 1 2 3 4 36 38 9 0 1 2 44 46 484950 3 3 3 35 37 3 4 4 4 43 45 47
Output I/F
VSSRAM2
YOUT8
YOUT7 YOUT6 YOUT5 YOUT4
VSSIO2
output I/F
TC90A92AFG
3. Terminal description
Pin No. Pin Name Function Durabl e I/O voltage (V) 2.5 VDD 2.5 IN 2.5 Bypass 0 GND 3.3 VDD 3.3 IN 3.3 OUT 0 GND 3.3 IN 1.5 3.3 VDD IN Circuit System (Analog or Digtal) Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Digital DC of standard operation *iu*j 2.5 1.25 1.2 0 3.3 0 1.5 Analog signal effective level *iVp-p*j 0.5*VDDPLL*0.8 -
1 2 3 4 5 6 7 8 9
VDDPLL PLLIN VCOFIL VSSPLL VDDXO XOIN XOOUT VSSXO BUSSEL
10 DVDD1 11 DIN9
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
DIN8 DIN7 DVSS12 DIN6 DIN5 DVDD2 DIN4 DIN3 VSSRAM1 VDDRAM1 DIN2 DIN1 VDDIO1 DIN0 GC14IN
Power supply for X8 PLL circuit Input terminal of X8 PLL circuit Filter terminal for X8 PLL circuit GND for X8 PLL circuit Power supply for X' tal OSC circuit X' tal OSC circuit input terminal X' tal OSC circuit output terminal GND for X' tal OSC circuit Select IIC slave address *i B0 Hi*F L*F B2*j Power supply for Logic circuit Composite video signal digital input terminal (MSB) *i DIN0*DIN9*F input terminal for GR*j *i case not use :DIN0-9 are connected to GND*j In Composite video signal digital input terminal GND for Logic circuit Composite video signal digital input terminal Power supply for Logic circuit Composite video signal digital input terminal GND for internal DRAM Power supply for internal DRAM Composite video signal digital input terminal
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSSIO1 TESTIN TESTM0 RESET SDA SCL TESTM1 TESTM2 TESTM3 DVDD3 TESTM4 CSYNCIN DVSS3 TESTM5 TESTM6 VDDIO2 YOUT9
Power supply for I/O Composite video signal digital input terminal External 4fsc clock input terminal for Using DIN0-9 terminal *i case not use : connect to GND*j In GND for I/O Clock terminal for Test mode Terminal for Test mode Reset terminal (Low :Reset Hi :normal) bhh r c terminal (5V input possible*j bhh rk b terminal (5V input possible) Terminal for Test mode
3.3 3.3 0 3.3 3.3 1.5 3.3 3.3 0 1.5 3.3 3.3 3.3 3.3 3.3
IN IN GND IN IN VDD IN IN GNG VDD IN IN VDD IN IN
Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital
0 1.5 0 1.5 3.3 -
-
Power supply for Logic circuit Terminal for Test mode External composite Sync signal input GND for Logic circuit Terminal for Test mode Power supply for I/O Digital video port output*i MSB*j *i 656/ 601 8bit mode*F YCbCr 601*F Y*j Digital video port output8 GND for I/O Digital video port output7 Digital video port output6 Digital video port output5 Digital video port output4 GND for internal DRAM
0 3.3 3.3 3.3 5 5 3.3 3.3 3.3 1.5 3.3 5 0 3.3 3.3 3.3 3.3 3.3 0 3.3 3.3 3.3 3.3 0
GND IN IN IN I/O IN IN IN IN VDD IN IN GND IN IN VDD OUT OUT GND OUT OUT OUT OUT GND
Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital
0 0 0 3.3 0 0 0 1.5 0 0 0 0 0 3.3 0 0
-
YOUT8 VSSIO2 YOUT7 YOUT6 YOUT5 YOUT4 VSSRAM2
TC90A92AFG
Pin No. Pin Name Function Durabl e voltage (V) 1.5 0 2.5 3.3 3.3 3.3 3.3 3.3 1.5 3.3 I/O Circuit System (Analog or Digtal) Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital DC of standard operation *iu*j 1.5 0 2.5 1.5 Analog signal effective level *iVp-p*j -
51 52 53 54 55 56
VDDRAM2 VSSRAMD1 VDDRAMD1 YOUT3 YOUT2 YOUT1
Power supply for internal DRAM GND for internal DRAM Power supply for internal DRAM Digital video port output Digital video port output (In case 8bit output mode : fixed to Low) System Clock output terminal for digital video signal output 656 : 27MHz 601 : 13.5MHz Power supply for Logic circuit bbbr digital video signal output (LSB*j *i 656*F Low 601*F fixed CbCr*j *i case 16bit mode: LSB and 2'nd LSB are fixed Low) In GND for Logic circuit bbbr digital video signal output Power supply for I/O bbbr digital video signal output GND for I/O bbbr digital video signal output Power supply for Logic circuit bbbr digital video signal output GND for Logic circuit bbbr digital video signal output *i MSB*j Horizontal reference timing pulse Vertical reference timing pulse Field detection output / Pedestal pulse output Reference pulse of multiplexed Cb/Cr signal Reference pulse of IIC read for VBI data slice Function (Hi level at 23 line and 286 line) Clamp signal for YIN The bias terminal for internal 10bit ADC The reference top voltage terminal of internal 10bit ADC The reference middle voltage terminal of Internal 10bit ADC GND for internal 10bit ADC Analog CVBS/Y signal input terminal for Internal 10bit ADC Power supply for internal 10bit ADC The reference bottom voltage terminal of Internal 10bit ADC The bias terminal for internal 8bit ADC The reference top voltage terminal of Internal 8bit ADC Analog C signal input terminal for Internal 8bit ADC Power supply for internal 8bit ADC Analog Cr signal input terminal for Internal 8bit ADC GND for internal 8bit ADC Analog Cb signal input terminal for Internal 8bit ADC The reference bottom voltage terminal of internal 8bit ADC Power supply for internal DAC of NCO Output terminal of DAC of NCO GND for internal DAC of NCO The bias terminal for internal DAC The reference voltage terminal of DAC
VDD GND VDD OUT OUT OUT OUT OUT VDD OUT
57 YOUT0 58 CKOUT 59 DVDD4 60 COUT0
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
COUT1 DVSS4 COUT2 VDDIO3 COUT3 COUT4 VSSIO3 COUT5 COUT6 DVDD5 COUT7 COUT8 DVSS5 COUT9 HDOUT VDOUT OEPK UVFLAG VBIREADY
3.3 0 3.3 3.3 3.3 3.3 0 3.3 3.3 1.5 3.3 3.3 0 3.3 3.3 3.3 3.3 3.3 3.3 3.3 2.5 2.5 2.5 0 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 0 2.5 2.5 2.5 2.5 0 2.5 2.5
OUT GND OUT VDD OUT OUT GND OUT OUT VDD OUT OUT GND OUT OUT OUT OUT OUT OUT OUT Bypass Bypass Bypass GND IN VDD Bypass Bypass Bypass IN VDD IN GND IN Bypass VDD OUT GND Bypass Bypass
Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog
0 3.3 0 1.5 0 0.8 1.75 1.25 0 2.5 0.75 0.8 1.75 1.25 2.5 0 0.75 2.5 2 0 0.9 1.5
VDDYADx0.4 VDDCADx0.4 VDDCADx0.4 VDDCADx0.4 VDDDA -VDDDA*0. 6 -
80 YCLAMPP 81 BIASYAD 82 VRTYAD 83 VRMYAD 84 VSSYAD 85 YIN 86 VDDYAD 87 VRBYAD 88 BIASCAD 89 VRTCAD 90 CIN 91 VDDCAD 92 CRIN 93 VSSCAD 94 CBIN 95 VRBCAD 96 VDDDA 97 DAOUT 98 VSSDA 99 BIASDA 100 VREFDA
(Note) Please the capacitor of the power supply terminal and the BIASAD terminal is placed near the terminal.
TC90A92AFG
4.1 Introduction
TC90A92AFG is a signal processor for normal scan (525i, 625i) signal. 1. TC90A92AFG has input interface for CVBS, S and component video signals. 2. TC90A92AFG has a 3D YCS function for M-NTSC signal with internal 4Mbit DRAM. And in case of 3line YCS mode it is available to use 3D YNR & CNR function. 3. TC90A92AFG has a 3D YNR & CNR for S terminal input and 1H component signal. 4. TC90A92AFG has a digital input interface for Ghost reduction LSI. 5. TC90A92AGF has color decoder circuit for multi video system and cync separation circuit. 6. Selectable automatic color system detection mode and forced color system mode. 7. TC90A92AFG has picture quality improve function. 8. TC90A92AFG has ITUR-656 and 601 output interface. 9. TC90A92AFG has S/N detection, ID-1 data slice and CCD data slice function for M-NTSC and it is available to read via IIC read mode.
4.2 Function
(1) Input stage The input video signal (CVBS/S / YCbCr) is converted to digital video signal by internal A/D converter of TC90A92AFG. TC90A92AFG generates the fH synchronous clock (27MHz) from the digital video signal by using PLL circuit, H sync separation circuit and H sync regeneration circuit. This clock is generated by internal digital VCO circuit which has 42MHz X'tal oscillation circuit as a reference clock. (2) Input interface a) Setting for input mode Input signal can be set via INSEL at sub address 00 hex. INSEL : 00: CVBS 01: S input 10: YCbCr 11: GR digital input b) Dynamic range of the internal ADC TC90A92AFG has a 10bit ADC for analog CVBS, Y signal of S input and Y signal of component. For color signal (chroma & CbCr), TC90A92AFG has a another 8bit ADC. Dynamic range of the internal ADC is designed by AVDD*~ 0.4(Reference level : 1Vp-p). Recommend amplitude of analog video signal input is 0.7Vp-p (140IRE).
TC90A92AFG
100 80 60 40 20 0 -20 -40 Fig-1 : YAD Input Level (Example : CVBS Input )
767
256
52
Fig-2 : CAD Input Level (Example : Cb Input Signal) When using YCbCr mode, it is cautious of the input level to CAD (color system 8bit AD). As shown in Fig-2, the standard input level of the CAD is 0.7Vp-p.
c) Clamping The clamp control circuit controls the correct clamping of the analog input signals. Clamp level for CVBS and Y signal is 256 LSB (10bit unit). For C and Cb/Cr are 128 LSB (8bit unit). d) Cb /Cr input Cb and Cr signals are multiplexed in front of internal 8bit ADC. Offset adjustment is available independently.
1023
0
TC90A92AFG
(4) TV system detection for CVBS and S input TV system auto detection is set via register [AUTODET] at sub address 00 hex. 00 : forced TV mode (color system is set via [TVM ] at sub address 00 hex. It is fixed to color system which is selected by [Select FSC], [Select FV], [Select PAL], [Select SECAM]. When there is difference between selected TV system and input TV system, it can't detect fsc signal for read mode. There is no relation to setting [Select FV] and input signal gives priority. 01 : European mode (fsc detection : 4.43MHz / 3.58MHz) Color system is determined by result of vertical frequency detection, fsc detection, SECAM detection. The order of priority for distinction is 4.43PAL, NTSC, SECAM, ACK. 10 : South American mode (fsc detection : 3.57954MHz /3.5756MHz /3.5820MHz) Color system is determined by result of fsc detection, vertical frequency detection. The order of priority for distinction is 3.58PAL, 3.58NTSC, ACK. 11 : full multi mode Color system is determined by result of vertical frequency detection, fsc detection, SECAM detection. The order of priority for distinction is PAL, NTSC, SECAM, ACK. And the distinction of 50/60Hz are independently, there is no priority. (In case of non signal, it keeps the value of last time.) (5) Sync processing TC90A92AFG has a H/V sync separation circuit and regenerates HD/VD pulse. The phase of HD and VD signals are selectable. (Adapt to 656 format and synchronized with input signal phase) (6) Y/C separation and noise reduction TC90A92AFG has an adaptive comb filter and noise reduction circuit. M-NTSC : Motion adaptive 3D comb (The sensitivity of motion detection for Y & C are set independently.) Other color system (Not M-NTSC and not SECAM) : 3D YNR and CNR after 3line comb SECAM : BPF+3D YNR. 3D CNR is simple motion (Not edge detection). The function is shown in a table-1.
TV signal PAL N PAL SECAM NTSC-50 Component-5 0 M NTSC 4.43NTSC M PAL PAL-60 SECAM-60 Component-6 0 Field Frequenc y Input signal CVBS 2DYCS+3DYNR+3DCNR 2DYCS or BPF+3DYNR+3DCNR BPF +3DYNR 2DYCS or BPF+3DYNR+3DCNR *| 3DYCS or 2DYCS+3DYNR+3DCNR 2DYCS or BPF+3DYNR+3DCNR 2DYCS or BPF+3DYNR+3DCNR 2DYCS or BPF+3DYNR+3DCNR BPF +3DYNR *| S 3DYNR+3DCNR 3DYNR+3DCNR 3DYNR 3DYNR+3DCNR *| 3DYNR+3DCNR 3DYNR+3DCNR 3DYNR+3DCNR 3DYNR+3DCNR 3DYNR *| YCbCr *| *| *| 3DYNR+3DCNR *| *| *| *| 3DYNR+3DCNR
50Hz
60Hz
Table-1 Note : Field noise reduction for 625 system
TC90A92AFG
(7) Take off filter (TOF) TC90A92AFG has a take off filter in front of internal color decoder. Characteristic of TOF is set via [TOF] at sub address 0F hex. 000 : OFF 001 : BPF for cross color reduction is active. 010 -111*Ftype2 - type7 (8) Y process a) Vertical enhance : available to set coring, gain and non-linear performance b) LTI function f0 is selectable (3.3MHz/ 2.2MHz). Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE). Gain is selectable (OFF/ x1/8 / x1/4 / x1/2). c) Sharpness f0 is selectable (4.2MHz/ 3.3MHz). Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE). Gain is selectable (OFF/ x1/8 / x1/4 / x1/2). d) Noise chancellor f0 is 4.2MHz. Gain is selectable (OFF/ x1/4 / x1/2 / x1). Coring level is selectable (0.8IRE/ 1.6IRE/ 3.2IRE/ 6.4IRE). LTI
*{
Sharpness Noise cancel /Gain/Coring 0 /Gain/Coring 0 e) Contrast Control range is -6dB --- +7.6dB (The color becomes a saturation depending on input level.) f) Brightness control Control range is 0LSB ---+ 60LSB (10bit unit) Brightness control is effective at the period of picture area. (9) C process a) ACC control : A reference level is set up by register ACC LEVEL. (Recommended value is under 3) b) Killer control : sensitivity of killer is set via [COLOR KILL LEVEL] at sub address 0E hex. In case Killer detection, comb filter for Y becomes off. c) HUE control : Hue control is available for CVBS and C signal of NTSC system. Hue bias : 0 --- +45degree Hue range : -45 degree --- +43.6degree Base band Tint control is available for component signal input mode. Hue range : -45 degree --- +43.6degree
TC90A92AFG
d)Sub color gain control Amplitude of Cb and Cr signals are controlled via IIC. Control range is -6dB --- +2.8dB e)CTI function f0 is selectable (1.7MHz/ 3.3MHz). Coring level is selectable (0.4IRE/ 0.8IRE/ 1.6IRE/ 3.2IRE). Gain is selectable (OFF/ x1/8 / x1/4 / x1/2). f) Offset control of the period of picture area The DC level of the Cb and Cr signals are controlled via IIC independently. Control range : -8LSB ---- +7LSB (10bit unit) (10) Output format 656 output mode / 601 output mode (CKOUT *F polarity is selectable) the 8bit mode /10bit mode selectable Y *F pedestal = 16LSB (8bit unit) C *F 128LSB (8bit unit) (except the period of picture area) It is selectable 601 or 656 format at sub address 01hex :D4 [FORMATO] It can limit to the signal under 16LSB(in 8 bit) at sub address 23hex :D2 [CLP] In case of standard 656 output, it is necessary to set to limit. YOUT, COUT and CKOUT can be set Hi-Z mode via IIC.
Pin YOUT [0-9] 8 COUT [0-9] / Bit 8/10 1 8/10 Data rate 13.5MHz/27MHz
Comment 601mode:Y signal 656 mode: YCbCr (CK:27MHz)8/10 8/10CKw 0 38/10 0 8/10 8/108/10 8/108/10 6.75MHz e38.5 415.388081 T 95 Cb/Cr (CK:13.5MHz) Tw ( ) Tj 121.5UVFLAG61 Tc 0.1234 :13.5MHz) 8/10 601mod
TC90A92AFG
a) Vertical output timing a-1 ) 525 /60Hz input (first field) ba ur TT Q P Q R S T U V W X PO *c PX QO
g ns ct
Sync through Mode
un cs t
nc c
/dd um
FIELD 1
656 Mode
un cs t
n c
/dm d u
FIELD 1
(2n'd field)
br u a
gt cs n us c n t
Sync through Mode 656 Mode
nc c
/d u d m
FIELD 2
un ct s nc c /dd um FIELD 2
TC90A92AFG
a-2 ) 625/50Hz input mode *i first, 3thd field*j ba ur UQP UQ Q UR Q US Q UQT P Q R S T U *c QQ QR
gn cs t un cs t
Sync through Mode 656 Mode
nc c
/dm u d
FIELD 1
uns ct nc c /dd u m FIELD 1
(2'nd 4thd field)
ba ur
RX O
RO P
RPP RPQ RR P
RS P
RT RU P P
R V RPW RPX P
*c
RRT RRU
gns c t
Sync through Mode
un ct s nc c
un ct s nc c /dd u m FIELD 2 /dd u m FIELD 2
656 Mode
Width of HD and VD pulse at Sync through mode 525 625 HD pulse 4.74us (128ck at 27MHz) VD pulse 3H 2.5H Width of HD pulse at 656 format is the same as the period between EAV and SAV. In case of input signal is non standard at 656 format, it may not be above value.
TC90A92AFG
(11) Feature function a) S/N detection Noise detection is performed in the vertical blanking period. Detection is performed at every field and the data is updated each field. A S/N detection result is 8bit data and it can be read via IIC. b)ID-1 data slice function TC90A92AFG has a data slice circuit for ID-1 signal at the line 20 and 283. Sliced data can be read via IIC. This function is only output of sliced data level. It is necessary to check a continuation of signal between some fields for ID-1 signal detection. c) CCD data slice function TC90A92AFG has a data slice circuit for closed caption data at the line 21 and 284. CRI detection, start bit detection and sliced data can be read via IIC. VBI READY (Pin79) is a reference timing pulse for S/N detection and VBI data slice function. VBI READY outputs Hi pulse at the line 23 and 286. d)Others TC90A92AFG has IIC read registers. 50/60Hz detection/ signal detection / V sync detection / locked unlocked detection / 4.43MHz fsc detection / PAL detection / SECAM detection / Killer detection
TC90A92AFG
5.IIC BUS The slave address of TC90A92AFG can use two, B0hex and B2hex. A slave address is chosen by BUS SELL of a terminal 9 (BUS SELL=L:B0hex , BUS SELL=H:B2hex). In addition to usual transmission, a transmission format can use continuation transmission and the auto increment mode. (a) Continuation transmission *iThe sub-address of a register to change is specified. MSB of a sub-address is set to 0 at this time.*j S Slave ADD 0 A Sub ADD a Sub ADD b A A DATA 7-0 DATA 7-0 A A
(b) Auto increment *iThe increment of the sub-address is carried out one by one from N. MSB of a sub-address is set to 1 at this time.*j S Slave ADD 0 A Sub ADD n (Sub ADD n+1*j A DATA 7-0 DATA 7-0 A A
(c) IIC read If it sets to 1 for LSB of slave address , it can read data. It starts data output from TC90A92AFG after TC90A92F is the master and the micro controller is slave. To suspend transmission, deliberately generate an acknowledge error. S Slave ADD (R) 0 A DATA 07-00 DATA 17-10 A A DATA 0F-08 DATA 1F-18 A A
TC90A92AFG
I2C BUS control format outline The BUS control format of TC90A92F is based on the PHILIPSI2C BUS control format. Data transmission format
S
Slave Address
7bit
0A
Sub Address
A
Data
AP
S: Start conditions P: Stop conditions A: Acknowledgement
*
MSB
* 8bit
MSB
* 8bit
MSB
(1) Start conditions, Stop conditions SDA
(2) Bit transmission SDA
SCL
S
Start conditions
P
Stop conditions
SCL
SDA is not changed.
SDA is changed.
(3) Acknowledgement
SDA from a master High impedance
SCL from a master S Start conditions
1
8
9
A6 A5 A4 101 1 A6 A5 A4 101
A3 A2 A1 A0 R/W 1000 X A3 A2 A1 A0 R/W 1000 X
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
TC90A92AFG
IIC BUS MAP
Sub 00H D6 INSEL Select input signal 00:CVS (Composite Signal*j 01:Y/C *i Sep. Signal*j Y/C 10:YCbCr *i Component signal*j 11:4fsc Data *i Digital Signal*j D7 D5 D4 TVM3 TVM2 Select FSC Select FV 0*F 3.58MHz 0*F 60Hz 1*F 4.43MHz P*F 50Hz 0000*F NT358 0100*F NT50 0001*F don't use 0101*F don't use 0010*F PAL-M 0110*F PAL-N 0011*F don't use 0111*F don't use YCS Mode YCS mode D3 TVM1 Select PAL 0*F PAL Not 1*F PAL 1000*F NT443 1001*F SEC60 1010*F PAL60 1011*F don't use FORMATO Output format D2 TVM0 Select SECAM 0*F SECAM Not 1*F SECAM 1100*F don't use 1101*F SECAM 1110*F PAL 1111*F don't use OUTBITS D0 AUTODET Set detection mode for Video System 00:Manual *i 00h-D5-D2*j 01:European 10:South America 11:Full multi HIZMODE Output control ADPWD D1
INIT:03H 01H
3D DET Preset mode
TC90A92AFG
D6 D5 D4 D3 D2 D1 D0 ACMSLP ACSSLP AYMSLP AYSSLP C slope at 1F (motion scene) C slope at 1F (still picture scene) Y slope at 1F (motion scene) Y slope at 1F (still picture scene) INIT:5DH 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * 11H ACMESET ACMFSET ACSESET ACSFSET C offset at 1F(edge*C motion) C offset at 1F (flat*C motion) C offset at 1F (edge*C still) C offset at 1F (flat*C still) INIT:AAH 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 12H AYMESET AYMFSET AYSESET AYSFSET Y offset at 1F(edge*C motion) Y offset at 1F (flat*C motion) Y offset at 1F (edge*C still) Y offset at 1F (flat*C still) INIT:AAH 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 13H BCMSLP BCSSLP BYMSLP BYSSLP C slope at 2F (motion scene) C slope at 2F (still picture scene) Y slope at 2F (motion scene) Y slope at 2F (still picture scene) 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * 00*F * 11*F x1/2 * INIT:49H *k YCSOA IY --LOEo *l *k YCSOA IY --LOEo *l 14H BCMESET BCMFSET BCS ESET BCSFSET C offset at 2F(edge*C motion) C offset at 2F (flat*C motion) C offset at 2F (edge*C still) C offset at 2F (flat*C still) INIT:51H 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 15H BYMESET BYMFSET BYSESET BYSFSET Y offset at 2F(edge*C motion) Y offset at 2F (flat*C motion) Y offset at 2F (edge*C still) Y offset at 2F (flat*C still) 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel 00*F pixel*11*F still motion pixel INIT:F5H 16H BCMUP CECMP CSCMP C 2F Motion The reference level for C edge detection The reference level for C signal detection detection 0*F ON 000*F small * 111*F large 0000*F small * 1111*F large INIT:C3H 1*F OFF *k NR mode *l for 17H F1HER F1VER MREF Level for Y horizontal edge Level for Y vertical edge The reference level for scene detection 00*F OFF 10*FIRE 3 00*F OFF 10*FIRE 5 0000*F small * 1111*F large INIT:A4H 01*FIRE 6 11*F 1.5IRE 01*F IRE 12 11*FIRE 2 18H CDEYE YDEYE MDS 3DSTD Reference level for scene det. Reference level for scene det. Y Forced det. Forced det. C 00*F 8% 10*F 24% 00*F 8% 10*F 24% 0*F normal Fixed to [0] Fixed to [0] 0*F normal INIT:10H 01*F 16% 11*F 32% 01*F 16% 11*F 32% 1*F still 1*F sig. std 19H 2ASS 2ASEL 2ALEV 2ASSCM CROS 2F motion det. 2F motion det. 2F motion det. judgment level 2F motion det. of C motion Reduce Correction Select Cross color 0*F OFF 0:Y 000:OFF 00:motion pixel * 11:still pixel 0:ON INIT:BEH 1*F ON 1:C 001:motion pixel * 111:still pixel 1:OFF 1AH CHLPF YDCLOFF YDNRW CDNRW YDCMP[3:0] Band width NR Sensitivity Y Sensitivity C The reference level Y motion detection for *k NR*l Non correlation Non correlation 0: wide 0*F OFF 0*F large 0*F large 0000:motion * 1111:still*k 1000*l INIT:08H 1: narrow 1*F Non-linear 1*F small 1*F small 1BH HDAMP1 HD GAIN1 Time constant 1 for H PLL Loop gain 1 for H PLL INIT:89H 000*F large * 111*F small 00000*F small * 11111*F large 1CH HDAMP2 HDGAIN2 Time constant 2 for H PLL Loop gain 2 for H PLL INIT:88H 000*F large * 111*F small 00000*F small * 11111*F large 1DH HDAMP3 HDGAIN3 Time constant 3 for H PLL Loop gain 3 for H PLL INIT:A2H 000*F large * 111*F small 00000*F small * 11111*F large 1EH SHCTRL MUTE C MUTE H Reference Mute Chroma mute 100000*F -4.74E * 000000*F " *}0E * 011111*F " +4.46E " 0*F OFF 0*F OFF INIT:00H 1*F ON 1*F ON 1FH DOT DIST COMB+ 1LINE DOT BCFOFF CGAIN Reduce H dots BSRC filter x trap performance for SECAM 00*F OFF 10* 0.17 F 0*F OFF 0:ON 0: ON 000*F OFF * P *F 0.875 (INT:110) P P *~ INIT:FEH 01* 0.16 F 11* 0.18 F 1*F ON 1:OFF 1:OFF Sub 10H D7
TC90A92AFG
Sub 20H INIT:8BH 21H D1 D0 CCDSBH CCD start bit (H pulse period) OO OO 1111:30CK*0000:0CK (*CK=74ns) FIV FON Field for CCD slice Fixed [0] *mFNormal 0* n * Fixed [1] Fixed [0] Fixed [1] Fixed [1] CCD slice action *mFON 1* n * 0:EVEN 0:both field 1:ODD 1:FIV EN_NOISEH_S EN_NOISEH_W SSMSB AUTO The horizontal start timing of S/N detection The horizontal width of S/N detection CCD slice 000*F 35.7uS * 100*F +40.5uS * 111*F 44uS 000*F 10.2uS * 100*F 14.9uS * 111*F 18.5uS Fixed to[1] 0:Auto (1step: 32/27MHz) (1step: 32/27MHz) 1:manual EN_NOISEV_S EN_NOISEV_W CLP BYFOFF BLMT Adjustment for S/N detection start line S/N detection line number 16LSB limit BSRY filter V sepa. (Ex. NTSC mode) (output) Limit 2Fh(D3)=0, 000*F line*111*F line 12th 18th 00*F 01*F 10*F 11*F 1H*A 2H*A 3H*A 4H 0:OFF 0:ON 0: 1/8 2Fh(D3)=1, 000*F line*111*F line 7th 13th 1:ON 1:OFF 1: 1/16 HDPH VDPH Adjustment Horizontal phase Adjustment vertical phase 1000*F -1.185uS * 0000*F 0uS * 0111*F +1.04uS 0000*F * 1111*F 0H +15H VPHS CADSWREV HDST SELCK VDOUT adjustment (601 mode) Cb/Cr Input HDOUT adjustment (601) CKOUT frequency 110:384w 011:192w 000:0w 0*F Pin92=Cr- IN, 10:TEST 00:13.5MHz 111:don't use 100:256w 001:64w (See p.23) 11:13.5MHz 01::27MHz Pin94=Cb- IN 101:320w 010:128w 1*F Pin92=Cb- IN, 64W=64/27MHz=2.4uS Pin94=Cr-IN PHPOLE HDOUT polarity 0: positive 1:negative PVPOLE VDOUT polarity D7 D5 D4 ID1DLY The start timing ch P data slice of *F Falling edge of H +P*D E * *i Z unit*j S W " 300 " 8OUTLSB D6 D3 D2
INIT:80H 22H
INIT:90H 23H
INIT:0AH 24H INIT:00H 25H
INIT:03H 26H
PFPOLE THRHV INVCK SEL_BLK YOLEVEL HHKIL Field H,V-OUT CKOUT VBLK Y Output Half H killer Polarity through Polarity Level Select 0:positive 0:positive 0:656 0:positive 0:fixed value 0:x1.7 0*F OFF INIT:18H 1:negative 1:negative 1:through(601) 1:negative 1:through 1:x1.0 1*F ON 27H EN_PIXH_S EN_PIXH_W Adjustment horizontal signal processing (start phase) Adjustment horizontal signal processing (period) INIT:00H 1000*F -1.185E * 0000*F " center * 0111*F +1.04E " 1000*F -1.185E * 0000*F " center* 0111*F +1.04E " 28H EN_PIXV_S EN_PIXV_A COMB KILL Adjustment vertical signal processing (start phase) 0*F Manual 000*F OFF 011*F 1*23H 110*F 1*26H 0000*F 10 * 1111*F 25 line line 1*F Auto 001*F P*21H 100*F 1*24H 111*F Auto INIT:07H 010*F 1*22H 101*F 1*25H (60:22H,50:23H) 29H BFP_S SEL_RDATA Adjustment burst gate pulse start phas e [0] Fix Select read data INIT:00H 0000*F * 0111*F *}0 +4.44E (4/13.5M step) " (Reference the next page) 2AH HBLK_S HBLK_W Adjustment HBLK start phase Adjustment HBLK width INIT:00H 1000*F -2.37E * 0000*F * 0111*F " *}0 +2.07E " 1000*F -2.37E * 0000*F * 0111*F " *}0 +2.07E " 2BH FHST_S FVST_S Adjustment write timing for internal DRAM (horizontal) Adjustment write timing for internal DRAM (vertical) INIT:00H 1000*F -2.37E * 0000*F * 0111*F " *}0 +2.07E " 1000*F * 0000*F -8H center * 0111*F +7H 2CH EXTCLP SEL77 ACKDET IIRFIL Adjustment horizon position fine tuning for exterior clamp Pin77 Output Detection Cb/Cr output filter selection *i 6.75MHz unit*A Width 2.2us Fix*j change method change After input sync edge about +0.5E * about +3E s s 0:ODD/EVEN 0:Level detection 00:Strong * 10:weak INIT:B2H 1000*F +0.5E * 0111*F " " +3E 1:Clamp pulse 1:Gain detection 11:OFF 2DH GCSFT FBCLAMP GC Input DC shift F/B CLAMP 000000:O 1000000:-128lsb * 0111111:+126lsb *A 0:Auto INIT:01H 1:ON 2EH HGCON12 HGCON21 Threshold from phase difference big to middle. Threshold from phase difference middle to big. INIT:48H 0000:OFF * 1111:High 0000:OFF * 1111:High 2FH RBALT RBCHG YADFILON NOISESEL NOISEL THRH_VD ADC Output The line select S/N detection VD out phase Fixed [0] Fixed [0] 13.5M Trap Fixed [1] for S/N Line (It is available Fixed [1] 0:OFF 1:ON detection 0 : CVBS/Y when H-V is Effective only (See p.24) 1 : digital input Non-standard) at the time 0:standard INIT:00H of a CVBS input 1:V-sep phase
TC90A92AFG
READ MODE
07 *b 00 0F *b 08 17 *b 10 1F *b 18 27 *b 20 2F *b 28 37 *b 30 3F *b 38 DET50 Field frequency 0*F 60Hz 1*F 50Hz DET443 4.43Det. 0:non 1:4.43 NOSIG Sig.nal Det. 0*F signal 1*F signal no PALDET PAL Det. 0:not PAL 1:PAL NOVP V-Sync Det. 0*F det. V 1*F V non SECAMDET SECAM Det. 0:not SECAM 1:SECAM SNDET5 CFIELD Field 0*F ODD 1*F EVEN UNLOCK H-PLL 0*F un-locked 1*F locked H/VSTD H-V std 0:std. 1:non-std. CKILL Killer Det. 0:color 1:whit & black SNDET2 CRI3DET Fixed to [0] Fixed to [0]
SEL_FSC fsc detection 00:3.579545M 01:3.575611M 10:3.582056M 11:4.43M SNDET4 SNDET3
FSCSTD fsc std Det. 0:std 1:non-std SNDET1
FSCLOCK fsc lock 0:un-locked 1:lock SNDET0
SNDET7 SNDET6 S/N detection 00000000*F strong signal * 0 Fixed to [0] CFIELD Field 0*F ODD 1*F EVEN TSLV6
11111111*F Weak signal*i MSB*F SNDET7*j SBDET CCD SB Det. 0:NG 1:OK TSLV5 CRI3DET CCD CRI Det. 0:under 3ck 1:over 3ck TSLV4 CRIN3 CRIN2 Number of CRI TSLV3 TSLV2 CRIN1 (MSB)-----((LSB) TSLV1 TSLV0 CCD Slice Level (LSB) CCD data CRIN0
TSLV7 CCD Slice Level (MSB)
CCDD CharacterP CCD data LSB CCDD CharacterQ CCD data
CCD data MSB IICR ID1[2] ID1 bit0 (WORD0) IICR ID1[3] ID1 bit2 (WORD0) IICR ID1[4] ID1 bit3 (WORD1) IICR ID1[5] ID1 bit4 (WORD1) IICR ID1[6] ID1bit5 (WORD1) IICR ID1[7] ID1 bit6 (WORD1)
47 *b 40 4F *b 48 57 *b 50
IICR ID1[0] Reference Signal Detection 0:OK 1:NG IICR ID1[8] ID1 bit7 (WORD2) IICR ID1[16] ID1 bit15 (CRC code) IICR ID1[24] ID1 Slice level MSB*m *n V
IICR ID1[1] CRCA 0:OK 1:NG IICR ID1[9] ID1 bit8 (WORD2) IICR ID1[17] ID1 bit16 (CRC code) IICR ID1[25] ID1 Slice level
IICR ID1[10] ID1 bit9 (WORD2) IICR ID1[18] ID1 bit17 (CRC code) IICR ID1[26] ID1 Slice level
IICR ID1[11] ID1 bit10 (WORD2) IICR ID1[19] ID1 bit18 (CRC code) IICR ID1[27] ID1 Slice level
IICR ID1[12] ID1 bit11 (WORD2) IICR ID1[20] ID1 bit19 (CRC code) IICR ID1[28] ID1 Slice level
IICR ID1[13] ID1 bit12 (WORD2) IICR ID1[21] ID1 bit20 (CRC code) IICR ID1[29] ID1 Slice level
IICR ID1[14] ID1 bit13 (WORD2) IICR ID1[22] Fixed to[0]
IICR ID1[15] ID1 bit14 (WORD2) IICR ID1[23] Field det. 0:line 20 1:line 283 IICR ID1[31] ID1 Slice level LSB*m O*n
IICR ID1[30] ID1 Slice level
Select Read Data*i 29H*F D1,D0*j The initial of Read Mode is "00". SEL_RDAT 1byte 2byte A 00(Initial) D1 D0 01 D1 D0 10 D1 D0 11 I3 I2 3byte N0 C3 I3 I1 4byte C3 C2 I2 I0 5byte C2 C1 I1 D1 6byte C1 C0 I0 D0 7byte C0 N0 N0 N0 8byte I3 I3 C3 C3 9bite I2 I2 C2 C2 10byte I1 I1 C1 C1 11byte I0 I0 C0 C0
TC90A92AFG
The explanation for IIC Bus
*Sub address 00h(D7-D6), 01h(D0) ADC power save mode It can save the power automatically depending on the kind of input signal. When it is not use the ADC, it can stop working ADC. ADC Control 1 *k initial:00 *l Sub 00h D7 D6 00 01 10 11 ADC Control 2 *k initial:1 *l Sub 01h DO 0 1 Input signal It does not depend on the input signal. Y-ADC Power down Normal C-ADC Power down Normal Input signal CVBS Y/C Component Digital Y-ADC Normal Normal Normal Power save C-ADC Power save Normal Normal Power save
*Sub address 01h(D7-D6) 3D DET It can switch preset mode for motion detection. 00: Preset mode for 3D YC separation 01: Preset mode for 3D NR 10: 3 line comb mode (NR off) 11: manual mode (It is available sub address 10h - 1Ah)
*Sub address 01H(D5-D4) YC separation mode YC separation mode *k initial:00 *l Sub 01h D5 D4 00 01 10 11 3.58M NTSC system 3DYCS 3Line YCS + 3DNR BPF YCS + 3DNR 3Line YCS + 3DNR SECAM system BPF YCS + 3DNR BPF YCS + 3DNR BPF YCS + 3DNR BPF YCS + 3DNR Other system 3Line YCS + 3DNR 3Line YCS + 3DNR BPF YCS + 3DNR 3Line YCS + 3DNR
*E 3DYCS: 3D YC separation *E 3Line YCS: 3 line YC separation *E BPF YCS: Band Pass Filter YC separation *E 3DNR: 3D Noise Reduction
TC90A92AFG *Sub address 16h(D7) BCMUP
It can shift to motion seen for 2F motion detection of chroma signal. If BCMUP is on, it can decrease a dot noise for continuous color change. It must be attentive to increase a cross color noise when 2F motion detection for chroma is nearly motion. *Sub address 19h 2F correction It can control a phenomenon which the picture is in spite of still, it is treated as motion seen and appeared cross color noise. 19h(D7) 0:2F correction off 1:2F correction on 19h(D6) select a judgment standard signal 0:Working as base on motion detection result for 2F Y 1:Working as base on motion detection result for 2F C 19h(D5-D3) Setting a judgment level for working this function 000:off (same D7=0) 001:It is little effect : : 111:It is much effect 19h(D2) Setting motion detection for 2F correction 00: Moving picture direction : 11: Still picture direction Sub address 19h(D0) CROS In case of moving picture for high frequency of Y signal, it can reduce a cross color noise.
TC90A92AFG
*Sub address 1Ah
Motion detection for 3DNR
1Ah(D7) Select a band width for NR working 0:Wide band (Recommended) 1:Narrow band 1Ah(D6) When the picture is judged no color, it can control CNR motion detection for decreasing cross color noise. 0:motion detection for CNR is invalid. 1:Using still picture direction parameter 1Ah(D5) Setting non-correlation detection level for motion detection of Y 0:standard 1:two times of standard 1Ah(D4) Setting non-correlation detection level for motion detection of C 0:standard 1:two times of standard 1Ah(D3-D0) Setting Y signal moving amount judgment standard for NR 0000: Moving picture direction (There is little effect of decreasing cross color noise.) : 1111: Still picture direction (There is many effect of decreasing cross color noise.) *Sub address 1Fh(D5) COMB+ It has an effect as below for PAL system. When the horizontal lines of the front and the rear have color and edge element, and the horizontal line of center has no color, it drops Y signal level for calculated result. Therefore it occurs dots of black in spite of white and gray picture. When COMB+ is on, it can decrease this noise.
TC90A92AFG
*Sub address 24h Regarding digital output 24h(D7-D4) Setting horizontal phase for HDOUT When sync signal is the same timing as HDOUT, the difference phase is 0us. 24h(D3-D0) Setting vertical phase for VDOUT When vertical phase is 0H, timing diagram is as below. This is available for H,V-OUT through mode. (26h:D4=1)
ba ur gn cs t us c n t
*Sub address 25h(D7-D5) VPHS: Setting VDOUT phase When H,V-OUT through mode is on, it can shift VDOUT phase to horizontal direction. (2.4us step)
*Sub address 25h(D3-D2) HDST: Setting HDOUT phase When H,V-OUT through mode is on, it can shift HDOUT phase. It can delay HDOUT pulse from EAV based on standard. Regarding 525 lines system HDOUT phase (Default) It is 32W from first point of EAV. (1W=1/27MHz) HD width is about 4.73us. (128ck 1ck=1/27MHz) 00:32W(default) , 01:+4ck , 10:+8ck , 11:+16ck Regarding 625 lines system HDOUT phase (Default) It is 24W from first point of EAV. (1W=1/27MHz) HD width is about 4.73us. (128ck 1ck=1/27MHz) 00:24W(default) , 01:+4ck , 10:+8ck , 11:+16ck
*Sub address 26h(D5) PFPOLE,(D2) SEL_BLK 26h(D5) Setting field polarity When the polarity is positive, 1st field is low. 26h(D2) the disposal of blanking period 0:It is masked the signal under pedestal level. 1:Through
TC90A92AFG *Sub address 2Fh(D5) 13.5M Trap It can decrease the interference with 13.5MHz regarding to fh frequency and 14.3MHz regarding to fsc frequency. 0:OFF 1:ON (In this case, it needs to revise high frequency as below.) (The relation resister) Sub address 1Eh(D7-D2) Horizontal reference When input signal is CVBS, it needs to shift 1 step. (000000*111111) Sub address 04h(D1) Sharpness fo Sub address 05h(D7-D6) Sharpness gain If sharpness fo = 4.2MHz and sharpness gain = x1/8, the frequency characteristic is the same as trap-off.
*Sub address 22h*A Sub23h*A 2Fh(D3) Regarding noise detection 22h(D7-D5) Horizontal start phase from under direction edge of H sync 22h(D4-D2) Horizontal width 23h(D7-D5) Vertical start phase 23h(D4-D2) Vertical line number select *y1-A*zWhen sub address 2Fh (D3)=0, it is the start line number.
Sub address 23h (D7-D5) 000 001 010 011 100 101 110 111 ODD FIELD NTSC (Line number) PAL (Line number) 12 9 Non detection 10 13 11 14 12 15 13 16 14 17 15 18 16 EVEN FIELD NTSC (Line number) PAL (Line number) 274 321 275 322 276 323 277 324 278 325 279 326 280 327 281 328 EVEN FIELD NTSC (Line number) PAL (Line number) 269 316 270 317 271 318 272 319 273 320 274 321 275 322 276 323
*y1-B*z When sub address 2Fh (D3)=1, it is the start line number. ODD FIELD Sub address 23h (D7-D5) NTSC (Line number) PAL (Line number) 000 7 4 001 8 5 010 9 6 011 10 7 100 11 8 101 12 9 110 Non detection 10 111 13 11
TC90A92AFG *y Fig4*zThe line number for vertical period NTSC (525Line/60Hz) 1st Field (odd) 524525 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
NTSC (525Line/60Hz) 2nd Field (even) 261262 263264265266267268269 270271272273274275276277278279280281282283284285286 PAL (625Line/50Hz) 1st Field (odd) 621622 623624625 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PAL (625Line/50Hz) 2nd Field (even) 308309 310311312313314315316 317318319320321322323324325326327328329330331332333334335336337
*Sub address 2Fh(D2) Signal select for noise detection
TC90A92AFG *y Fig.5*z
TC90A92AFG the band limit characteristic for color decoder *i NTSC *j *i Marker* 3.58M*C F 4.286M*C 4.43MHz*j 10 5 Gain (dB) 0 -5 -10 -15 -20 0 1 2 3 4 Frequency *i * MH j 5 6 7
TC90A92AFG the band limit characteristic for color decoder*i PAL*j *i Marker* 3.58M*C F 4.286M*C 4.43MHz*j 10 5 Gain (dB) 0 -5 -10 -15 -20 0 1 2 3 4 Frequency *i * MH j 5 6 7
*Sub address 2Fh(D1) VD out phase select when H-V is non-standard and H,V-OUT is through mode. 0: standard phase (VD output after counted standard line number) 1: VD output as base on result of V-sep *Sub address 21h(D6) 8OUTLSB It can reduce quantization noise when 10 bit signal convert to 8 bit at output stage. This effect changes in GND condition. When output signal is 10 bit, it needs to set to normal mode. 0: Normal 1: ON (Quantization noise reduction is active.)
TC90A92AFG
MAXIMUN RATINGS*i Vss=0V, Ta=25*Z *j Each item of the maximum rating shows the marginal value of this product. Since a product is sometimes damaged when rating is exceeded also one item or for a moment again, be sure to use it within rating.
CHARACTERISTIC Power Supply Voltage1*i 1.5V System*j Power Supply Voltage2*i 2.5V System*j Power Supply Voltage3*i 3.3V System*j Input Voltage Potential difference between power terminals *i 1.5V System*j Potential difference between power terminals *i 2.5V System*j Potential difference between power terminals *i 3.3V System*j Potential difference between power terminals *i 1.5V System*2.5V System*j Potential difference between power terminals *i 2.5V System *3.3V System*j Power Dissipation Storage Temperature
SYNBOL VDD1 VDD2 VDD3 VIN SDA/SCL(Note1) A IN supply VDG1*i Note2*j supply VDG2*i Note2*j supply VDG3*i Note2*j supply VDG4*i Note2*j
UNIT RATING V -0.3 * VSS+2.0 V -0.3 * VSS+3.5 V -0.3 * VSS+3.9 -0.3 * VDDIO +0.3 V V -0.3 * VSS + 5.5 V -0.3 * VDDAD 0.3 V
0.3 0.3 0.3 0.3 1530 -40 * 125
V V V V mW *Z
supply VDG5*i Note2*j PD(Note3) Tstg
(Note1) SDA*C SCL*F5V tolerance. (Note2) 1.5V system power supply terminal is made into the same voltage, 2.5V system power supply terminal is made into the same voltage, and 3.3V system power supply terminal is made into the same voltage. The maximum potential difference should not exceed rating for all power supply terminals then. (Note3) Derated above Ta=25*Zin the proportion of 15.3mW/*Z .
Recommendation operation conditions*i Vss=0V*j Cannot guarantee operation of TC90A92F, when the recommendation power supply voltage range (1.35V-1.65V, 2.3V-2.7V, 3.0V-3.6V) is exceeded. Once, when it returns from the over range, it differs from a front condition. When the memory block exceeds the range especially, it is necessary to once bring down a power supply and to newly rise. CHARACTERISTIC Terminal No. SYNBOL MIN TYP MAX Supply Voltage for digital block 10,17,36,59,7 DVDD1-5 1.35 1.5 1.65
UNIT V V V V V V V *Z
0
Supply Voltage for I/O block 24,42,64 Supply Voltage for DRAM block 21,51 Supply Voltage for DRAM block 53 Supply Voltage for XO block 5 Supply Voltage for PLL block 1 Supply Voltage for Analog block 86,91,96 Ambient operating temperature VDDIO1-3 VDDRAM1 VDDRAM2 VDDXO VDDPLL VDDAD/VDDDA Ta 3.0 1.35 2.3 3.0 2.3 2.3 -10 3.3 1.5 2.5 3.3 2.5 2.5 *| 3.6 1.65 2.7 3.6 2.7 2.7 75
TC90A92AFG
The condition of power (VDD=3.3V, 2.5V, 1.5V) rising and falling
(1)Power Supply rising These contents are the important items which influence the reliability guarantee of the IC. It is necessary to satisfy the following condition.
(1) Power rising condition 3.3V (power range : 3.0 *3.6V) more than 3.0V
*note1 VDD=3.3V more than 0.4V
2.5V (power range : 2.3*2.7V) more than 2.3V
*note1 VDD=2.5V more than 0.4V 1.5V (power range : 1.35*1.65V) *note1 VDD=1.5V more than 0.4V It needs to rise less than 40ms from starting to rise the power of 2.5V. (using power on reset of DRAM ) (reset release) Terminal 30*F RESET After all powers rising, it is necessary to keep resett ing more than 0.5ms. And it must not keep the reset conditions more than one minute. IIC-Bus IN Terminal31*F SDA Terminal 32*F SCL After reset release, it is necessary to be more than 100ns for IIC BUS control starting. more than 1.35V
*note1 Such the power terminal are embedded the protective diode. It must not send a penetration electric current. Condition: Power level of 3.3V line * Power level of 2.5V line *Power level of 1.5V line When the power level of 1.5V line is more than 0.4V, 3.3V line and 2.5V line must reach the level of power more than 0.4V. And when the power level of 2.5V line is more than 0.4V, 3.3V line must reach the level of power more than 0.4V.
3.3V power terminal
2.5V power terminal
1.5V power terminal
(2) Power falling condition It is necessary to fall the power of 1.5V line before 3.3V line and 2.5V line are fallen, and to fall the power of 2.5V line before 3.3V line is fallen. It must not send a penetration electric current too.
TC90A92AFG
ELECTRICAL CHARACTERRISTICS
(1) DC CHARACTERRISTICS (Ta= -10*75*Z ,VDD1=1.50*}0.15V,VDD2=2.50*}0.2V,VDD3=3.30*}0.3V)
ITEM Power Supply Current Terminal No. 10,17,21,36,51,59,70 Symbol IDD1 Min. Typ. Max.
30 60 10
VDDx0.8
42 75 25
55 95 40
VDD
Unit mA
1,53,86,91,96
IDD2
mA
5,24,42,64
IDD3
mA
Input Voltage
6,9,11,12,13,15,16, 18,19,22,23,25,26, 28,29,30,33,34,35, 37,40,41 31,32,38
VIH
V
Note Sum total current of 1.5V system power supply terminal NTSC:Y/C IN, Color Bar Signal Sum total current of 2.5V system power supply terminal NTSC:Y/C IN, Color Bar Signal Sum total current of 3.3V system power supply terminal Changes with the loads of I/O. I/O input terminal of 3.3V system VDD=VDD3 I/O input terminal of 5.0V system VDD=5.25V I/O input terminal of 3.3V system
6,9,11,12,13,15,16, 18,19,22,23,25,26, 28,29,30,33,34,35, 37,40,41 31,32,38 Input Current 6,9,11,12,13,15,16, 18,19,22,23,25,26, 28,29,30,33,34,35, 37,40,41 31,32,38 6,9,11,12,13,15,16, 18,19,22,23,25,26, 28,29,30,33,34,35, 37,40,41 31,32,38 Output Voltage 43,44,46,47,48,49,54, 55,56,57,58,60,61,63, 65,66,68,69,71,72,74 75,76,77,78,79,80 43,44,46,47,48,49,54, 55,56,57,58,60,61,63, 65,66,68,69,71,72,74 75,76,77,78,79,80 31
VIL
VSS
VDD3x0. 2
V
IIH
-10
10
E A
I/O input terminal of 5.0V system 3 I/O input terminal of 3.3V system
IIL
-10
10
E A
I/O input terminal of 5.0V system I/O input terminal of 3.3V system
VOH
VDD3-0.6
VDD3
V
I/O input terminal of 5.0V system I/O output terminal of 3.3V system Load of 4mA inflow I/O output terminal of 3.3V system Load of 4mA inflow I/O output terminal of 5.0V system Load of 4mA inflow
VOL
VSS
0.4
V
TC90A92AFG
(2) AC CHARACTERRISTICS (Ta=25*Z ,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM Symbol Min. Typ. Max. Unit Note
AD input level for Y AD input level for C ADC differentiation error ADC integration error Output impedance
VYIN VCIN DLEa ILEa Zy
0.7 0.5 *}4 *}4 200
0.8 0.8
160
240
Vpp Vpp LSB LSB
White 100% Signal Cb/Cr input
(3) PLL CHARACTERRISTICS (Ta=25*Z ,VDD1=1.50V,VDD2=2.50V,VDD3=3.30V)
ITEM Symbol Min. Typ. Max. Unit Note
Drawing-in frequency range Operation input amplitude
fckN Vck
-50 0.3
0.5
50 2.0
kHz Vpp
Clock Amplitude:0.5Vp-p Standard clock frequency input
TC90A92AFG Application Circuit
LPF BUF 2.5V VRBCAD 0.01E 0.1E Cb IN 1.5k 2.5V DAOUT 100E VDDDA 0.01E VREFDA 0.01E BIASDA 0.01E VSSDA @ @ 1.2k 4p @
LPF
LPF
LPF BUF
VSSCAD Cr IN 0.1E VDDCAD 100E CIN 0.01E0.01E VRTCAD 0.01E BIASCAD 0.01E VRBYAD VDDYAD YIN 0.47E VSSYAD VRMYAD 0.01E VRTYAD 0.01E BIASYAD 0.01E 2.5V
BUF BUF 2.5V
@
100E
0.1E 0.1E 10099 98 97 96 95 9 4 93 9 2 9 1 9 0 8 9 88 87 86 8 5 84 8 3 82 8 1
@
TESTM6 VDDIO2 YOUT9(MSB) YOUT8
CSYNC IN DVSS3 TESTM5
SDA SCL TESTM1
VSSIO2
YOUT7 YOUT6 YOUT5 YOUT4 VSSRAM2
TESTM2 TESTM3 DVDD3 TESTM4
31 32 33 3 4 3 5 36 37 38 39 4 0 41 4 2 4 3 4 4 45 4 6 4 7 4 8 49 50 0.01E 47E 1.5V 0.01E A @ 3.3V A
5V A
4.7k 4.7k
0.01E
47E
28TESTIN 29TESTM0 3 0RESET
47E
2.5V 1 VDDPLL 100E 0.1E 2 PLLIN 0.01E 1500 * F 3 VCOFIL 4 VSSPLL @ 3.3V 5 VDDXO 6 XOIN 18p 12p 1.5E100 7 XOOUT 1000p 8 VSSXO A 3.3V 9 BUSSEL A 1.5V 10DVDD1 11DIN9(MSB) 12 DIN8 TC90A92AFG 13DIN7 14DVSS12 A 1 5DIN6 ODIN5 GC INPUT Terminal 17DVDD2 18DIN4 19DIN3 B 20VSSRAM1 1.5V 21VDDRAM1 0.01E 22DIN2 23DIN1 3.3V 0.01E 24 VDDIO1 25DIN0(LSB) 26 GC14IN 27 A VSSIO1 47E 0.01E 270k 0.01E 47E 0.01E 47E 47E
80 YCLAMPP 79 VBI READY UVFLAG 78 77 OEPK 76 VDOUT
HDOUT 75 74 COUT9(MSB) 73 DVSS5 COUT8 72 71 COUT7 70 DVDD5 COUT6 69 68 COUT5 67 VSSIO3 66 COUT4 65 COUT3 64 VDDIO3 63 COUT2 DVSS4 62 61 COUT1 60 COUT0 59 DVDD4 CKOUT 58 57 YOUT0 56 YOUT1 55 YOUT2
100p
@
560 18k A 0.01E 1.5V A 0.01E 3.3V A 0.01E 1.5V B @
54 YOUT3 53 VDDRAMD1 0.01E 2.5V 52 VSSRAMD1 B 51 VDDRAM2 1.5V
TC90A92AFG *oe PACKAGE DIMENSIONS
QFP100 P- 1420 0.65Q -
TC90A92AFG
Marking
TOSHIBA TC90A92AFG
JAPAN Lot Code Management Code of Factory
Explanation for lot code
Production management number Weekly code The first week of January is assigned the code number 01, the second week 02 etc. The last week of December is either 52 or 53. This is determined as follows. Provided that the 1st January does not fall on a Friday or Saturday, the week which runs from the final Sunday of the old year to the first Saturday of the new year is designated as the first week of the new year [01]. If the 1st January falls on a Friday or Saturday, the week which runs from the final Sunday of the old year to the first Saturday of the new year is designated as the 53rd week of the preceding year [53].
The year of manufacture (The last two digits for AD)
Mold material: Epoxy resin Lead material: Copper base alloy Lead surface treatment: Palladium plating Country of origin: Japan Works: TOSHIBA Ooita Works
TC90A92AFG
Packing of QFP100
- P- 1420 Tray
1.Device Holder
Unit: mm
Package Code QFP100 -0.65 -P -1420
Maximum Number of Packed Product 40 products/tray 200 products/carton 1200 products/container
2.Carton Indicator Silica gel 43 1 *} 1321 *} Label 338 3 *}
(Inner size) Carton
Packing Label Moisture -proof package (laminated aluminum ) Label
3.Shipping Containe r (Inner size)
161 3 *} Bar code 281 3 *} 367 } *3 Outer size W:291mm L:377mm H:176mm

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